DUAL-LAYER PROTECTED RSA-CRT ARCHITECTURE: GOPPA CODES FOR COMMUNICATION CHANNEL AND RRNS FOR FAULT INJECTION RESISTANCE

Abstract

The growing complexity of cyber threats and the increasing susceptibility of cryptographic hardware to fault injection attacks and communication channel disturbances require the development of integrated fault-tolerant cryptographic architectures. Although the Chinese Remainder Theorem optimization of the RSA algorithm (RSA-CRT) significantly accelerates modular exponentiation, it remains highly vulnerable to computational faults, where even a single induced error may reveal confidential information or compromise the private key. In addition, communication channels are exposed to random and burst errors that reduce the reliability of transmitted cryptographic data. Therefore, ensuring both computational integrity and transmission reliability is an important challenge for modern secure information systems.

This paper proposes a dual-protection architecture for RSA-CRT that combines computational fault tolerance with communication error correction. The first protection layer employs a Redundant Residue Number System (RRNS) consisting of three information moduli and two redundant moduli. The introduced redundancy enables the detection, localization, and correction of erroneous residues through a majority-voting reconstruction procedure while preserving the inherent parallelism of modular arithmetic. The second protection layer utilizes Reed–Solomon error-correcting codes over the Galois field GF(28)GF(2^8)GF(28) to protect transmitted data against channel noise and burst errors, thereby ensuring reliable delivery of encrypted information before cryptographic processing.

A software prototype of the proposed architecture was developed and experimentally evaluated under combined fault scenarios including communication channel errors and injected computational faults. The obtained results demonstrate reliable correction of transmission errors together with successful localization and recovery of corrupted modular residues during RSA-CRT execution. The obtained performance confirms that the proposed architecture achieves a favorable trade-off between fault tolerance and computational efficiency without significantly affecting the throughput of cryptographic operations. The proposed architecture extends conventional RSA-CRT implementations by integrating two complementary protection mechanisms operating at different stages of information processing. Such an approach improves the robustness of cryptographic systems against both communication errors and computational fault attacks and may be applied in secure embedded systems, industrial controllers, cyber-physical systems, and other security-critical applications requiring high reliability of public-key cryptography.